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cpu Model Interface

CPU capabilities

Variables

Name Type Description Required Constant Default
arch String Architecture:
* x86
* x86_64
* PPC
* PPC64
* ARM7
* MIPS
cores Integer Effective number of cores.
For bigLITTLE and similar,
effective number of cores is 2
rather than 4
ht Boolean Hyper Theading support
freq Integer Nominal frequence in MHz
turbo_freq Integer Maximal frequence in MHz
l1_cache Integer L1 cache size in kb
l2_cache Integer L2 cache size in kb
l3_cache Integer L3 cache size in kb